AEA Ignite Progress Report · 6 October 2026

Reconfigurable Quantum Materials for Low-Energy Electronics

From Lab to Fab: advancing a new low-energy transistor towards large-scale manufacturing (IG250200225)

M1Milestone 1 complete: large-scale channel-material growth
1.3 nmthree-layer hBN spacer, resolved by TEM
2.9×the bilayer's field response (ηmax 0.161 vs 0.055)
Yuefeng Yin, Kaijian Xing, Weiyao Zhao, Mike Klymenko, Michael S. Fuhrer, Nikhil V. Medhekar, Wayne Johnson, Thomas Wrappe, Stuart Douglas
Working principle

A thin spacer lets the field move the bands

Put a thin spacer between two semiconducting monolayers, and the Stark effect gets much stronger.

  • Stabiliser. The spacer holds the two atomically thin films apart and keeps the interface stable.
  • Decoupler. It drives the bilayer towards a degenerate, monolayer-like electronic structure.
  • Less screening. An out-of-plane field now shifts the two layers' bands against each other.

General rule: a Type-I (straddling) alignment. The spacer's VBM and CBM must enclose those of the active film; here MoS2 / hBN / MoS2.

wide gap spacer gap encloses MoS2 CBM VBM Eg Eg(E) E, out of plane MoS2 hBN spacer MoS2
No field: both MoS2 layers line up, and the wide-gap hBN encloses them. (→ apply a field)Field on: one layer's bands rise, the other's fall, so the channel gap shrinks.
Built on our background IP1Gap tuning of Dirac semimetal. Patent US11239073B22TQFET. Patent application PCT/AU2021/0513063NC-TQFET. Patent application PCT/AU2022/0513384BILAYER STRUCTURES FOR TRANSISTOR CHANNEL LAYERS. U.S. Patent Application No. 19/814,331
Device fabrication

Building the dual-gated transistor, layer by layer

SiO2/Si substrate
Bottom gate · Au 15 nm
hBN · ~20 nm
1L MoS2
hBN spacer
1L MoS2
hBN · ~20 nm
Top gate · Au 50 nm
300 °C · Ar · 2 h
200 °C · Ar · 2 h
  1. Pattern the electrodesAu bottom gate (15 nm), contacts (20 nm) and top gate (50 nm) on a sacrificial SiO2/Si wafer: photolithography, e-beam evaporation, lift-off.
  2. Laminate the bottom gatePicked up and laminated onto a pre-cleaned SiO2/Si substrate by PC-assisted dry transfer.
  3. Bottom dielectricA ~20 nm hBN flake, transferred on top the same way.
  4. Anneal300 °C in Ar for 2 hours.
  5. Build the channel1L MoS2 / hBN spacer / 1L MoS2 (or 1L and 2L MoS2 references) on the gate area, with van der Waals Au contacts.
  6. Anneal again200 °C in Ar for 2 hours.
  7. Top dielectric and gate~20 nm hBN and the Au top gate complete the dual-gated FET.

Every layer, metals included, is van der Waals-integrated: better contacts, lower gate leakage, higher yield.

Device performance · Fig. 1

Three channels, the same dual-gate design

Device performance · Fig. 1b, d, f

Reading the gate maps

Device performance · the comparison

Drag across: what the spacer changes

  1. BilayerContours stay nearly parallel across the bias space.
  2. With the spacerSame axes: the contours now bend sharply at high field.
  3. Side by sideDrag the divider to compare any region.

The spacer decouples the two monolayers and suppresses quantum-capacitance screening, so the field can shift the bands.

Bilayer MoS2 · Case #2MoS2/hBN/MoS2 · Case #3
Drag the divider, or press → to step
Characterisation · Fig. 2

From the device to its atomic layers

Materials modelling · Fig. 3a, b

The spacer roughly triples the field response

Maximum switching figure of merit, ηmax
MoS2 ML
0
Eg 1.80 → 1.80 eV at 0.1 eV/Å
MoS2 BL
0
Eg 1.30 → 1.29 eV
MoS2/hBN/MoS2
0
Eg 1.77 → 1.52 eV
2.9×the bilayer's band-gap response per unit channel thickness
DFT band gap vs out-of-plane field (Fig. 3a).
Materials modelling · Fig. 3c–h

Switch the field on: watch the bands

System Field
Summary

The milestone in one picture

  1. The deviceA dual-gated FET with a MoS2/hBN/MoS2 channel.
  2. Seen by TEMTwo MoS2 monolayers, 1.30 nm apart.
  3. Sharp responseContours bend strongly at high field.
  4. Bilayer referenceConventional bilayer: nearly straight.
  5. TogetherA much sharper field response than conventional bilayer MoS2.
Programme · 12 months

Milestone 1 delivered; Milestone 2 under way

M0M1M2M3M4M5M6M7M8M9M10M11M12Milestone 1Large-Scale Channel-Material Growth1M4 Device fabrication2M5 Device measurement3M6 CharacterisationMilestone 2Integration with Ferroelectric Layers andPrototype Device FabricationFocus on device modellingExperimental + modellingMilestones 3 & 4Intellectual Property and Risk ManagementCommercialisation Preparation and EngagementOngoing IP / risk management · Ongoing partner engagement123

Ferroelectric integration

Add ferroelectric layers to the channel for non-volatile switching, with device modelling to predict performance.

New collaborators

Expanding the R&D program, particularly in large-scale thin-film growth and device fabrication.

IP & commercialisation

Ongoing IP and risk management, and partner engagement with TQ Transistors.

Thank you

From Lab to Fab

A working MoS2/hBN/MoS2 transistor channel, with 2.9× the bilayer's field response.

Contact: Yuefeng Yin · yuefeng.yin@monash.edu